Lateral high-voltage MOS transistors including an n-type conductive channel are typically fabricated on wafers of p-type conductivity in the form of DMOS transistors in which a topology of the doped zones corresponds to a “double diffused” MOS (in short DMOS) transistor, wherein a drain region is of the same conductivity type as a well doping, that is, of an n-type conductivity. Lateral high-voltage MOS transistors having a p-type conductive channel, i.e. being complementary laterally high-voltage MOS transistors with respect to the previous type referred to, are typically formed on p-type conductive wafers in the form of drain extension transistors, in which drain and drift regions are of an inverse conductivity type compared to the n-well that is also present in this case. Both transistor types are commonly referred to as lateral high-voltage MOS transistors in the context of this application.
In lateral DMOS (LDMOS) transistors for applications at high electrical voltages it is known from US2003/0193067 A1 (FIG. 2) to use a so-called double RESURF structure. RESURF is the abbreviation of the English term reduced surface field.
From U.S. Pat. No. 5,627,398 a Hall effect sensor is known, which represents an element of an integrated CMOS circuit.
From WO 2004/025743 A2 a Hall effect sensor is known in which a structure of nested doped regions with alternating conductivity is provided in a semiconductor substrate. In this structure is an inner first doped region extending to the surface of the semiconductor substrate surrounded by a central doped region in the shape of a “U”, which in turn is surrounded by an outer doped region, also in the shape of a “U”. The central doped region comprises a buried active section forming a Hall plate.
The technical problem underlying the present invention is to provide a semiconductor device as specified above, which enables a particularly simple fabrication of the semiconductor device by means of an alternative structure of the Hall effect sensor.